As integrated circuits become more complex, the topography associated with the integrated circuits also becomes more complex, i.e., deviations from surface planarity become greater. The complex topography causes problems in manufacturing because, e.g., several levels of dielectrics and of metallizations are now frequently used in integrated circuit fabrication, and the topography becomes more complex as the number of levels increases. However, satisfactory metallizations are frequently difficult to obtain over very complicated topography due to factors, e.g. poor step coverage, which cause discontinuities in the metallization.
For this reason, as well as for other reasons, methods have been devised which planarize dielectric surfaces as preparation for subsequent processing steps. For example, mechanical polishing methods have been developed which yield generally good results but typically suffer from at least two drawbacks. First, particles are produced and, second, heat is generated. The particles may contaminate the devices being produced and the heat may undesirably alter device characteristics. Another method which has been developed is a planarization etchback. This method deposits a photoresist over a thick dielectric, typically a deposited oxide, and then etches back to produce a planar dielectric surface. The deposited photoresist has a planar surface and, because the etch has similar etch rates for the photoresist and the dielectric, the planar surface is retained by the etching process. However, the photoresist introduces sodium ions which are removed by a wet chemical etch thus adding complexity to the manufacturing process. Additionally, the wet etch etches low density oxides more rapidly than it etches high density oxides. This creates a problem because the oxide is not usually deposited with uniform density but rather has low density regions running in substantially vertical directions. Low density regions are most likely to be present when the oxide is deposited between closely spaced metal runners, such as are present in submicron lithography. The etch produces trenches in the low density regions, thereby resulting in a nonplanar surface.
There may also be situations in which a planar surface is desired which is only partially formed by a dielectric. For example, a planar surface formed by metal runners and a dielectric between the metal runners may be desired. That is, the surfaces of the dielectric and of the metal runners should be coplanar.